In modern communication systems, frequency synthesizers are often used to establish the frequencies necessary for system operation. For example, in the receive system of a cellular phone, the local oscillators (LOs) that provide the frequencies used by the mixers in the system are commonly implemented by using frequency synthesizers.
Typically, programming a frequency synthesizer requires an external processor, such as a microcontroller, an embedded microprocessor, or a baseband modem, to write multiple data words to the synthesizer's register bank. These data words are parameters needed by the synthesizer to configure the desired output frequency. In existing implementations, the data words are written by the microcontroller over a bus, such as a serial bus, and thus the programming time of the microcontroller performing multiple register writes can be relatively lengthy.
The microcontroller load time can cause performance issues when the synthesizer needs to frequently change the frequency it is generating. For example, in a time division duplex (TDD) communication system utilizing frequency division duplex (FDD), the transceiver performs transmit and receive functions in a time interleaved manner. If the transceiver is implemented using a single synthesizer, the synthesizers registers must first be written with values appropriate for the transmit frequency to do transmission. After the transmission is complete, the register bank of the dual function synthesizer must again be written with values appropriate for the receive frequency. Over a communication period, such as the duration of a phone call, the alternation between transmitting and receiving causes the microcontroller to reload the synthesizer register values repeatedly, thus resulting in lengthy and redundant write cycles as well as unnecessary power consumption. It is desirable to have a way to reduce the redundant register writes, thereby reducing configuration time and power.